TCSEN=0, DEBESEN=0, BRRSEN=0, AC12ESEN=0, CEBESEN=0, BGESEN=0, DINTSEN=0, CCSEN=0, CCESEN=0, DTOESEN=0, CTOESEN=0, CINSEN=0, CIESEN=0, CINTSEN=0, BWRSEN=0, DCESEN=0, DMAESEN=0, CRMSEN=0
Interrupt Status Enable Register
CCSEN | Command Complete Status Enable 0 (0): Masked 1 (1): Enabled |
TCSEN | Transfer Complete Status Enable 0 (0): Masked 1 (1): Enabled |
BGESEN | Block Gap Event Status Enable 0 (0): Masked 1 (1): Enabled |
DINTSEN | DMA Interrupt Status Enable 0 (0): Masked 1 (1): Enabled |
BWRSEN | Buffer Write Ready Status Enable 0 (0): Masked 1 (1): Enabled |
BRRSEN | Buffer Read Ready Status Enable 0 (0): Masked 1 (1): Enabled |
CINSEN | Card Insertion Status Enable 0 (0): Masked 1 (1): Enabled |
CRMSEN | Card Removal Status Enable 0 (0): Masked 1 (1): Enabled |
CINTSEN | Card Interrupt Status Enable 0 (0): Masked 1 (1): Enabled |
CTOESEN | Command Timeout Error Status Enable 0 (0): Masked 1 (1): Enabled |
CCESEN | Command CRC Error Status Enable 0 (0): Masked 1 (1): Enabled |
CEBESEN | Command End Bit Error Status Enable 0 (0): Masked 1 (1): Enabled |
CIESEN | Command Index Error Status Enable 0 (0): Masked 1 (1): Enabled |
DTOESEN | Data Timeout Error Status Enable 0 (0): Masked 1 (1): Enabled |
DCESEN | Data CRC Error Status Enable 0 (0): Masked 1 (1): Enabled |
DEBESEN | Data End Bit Error Status Enable 0 (0): Masked 1 (1): Enabled |
AC12ESEN | Auto CMD12 Error Status Enable 0 (0): Masked 1 (1): Enabled |
DMAESEN | DMA Error Status Enable 0 (0): Masked 1 (1): Enabled |